diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-06-09 11:59:00 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-14 09:32:34 +0000 |
| commit | b0f1988f893bf5f581917816b11e810309955143 (patch) | |
| tree | c4bcf6f1d9384b99cfcbfab4426de9f9f106e720 /src/southbridge/intel/i82870 | |
| parent | 68c851bcd702e7816cdb6e504f7386ec404ecf13 (diff) | |
src: Get rid of unneeded whitespace
Change-Id: I630d49ab504d9f6e052806b516a600fa41b9a8da
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82870')
| -rw-r--r-- | src/southbridge/intel/i82870/82870.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82870/82870.h b/src/southbridge/intel/i82870/82870.h index 84ae47d3ef..1fe40b6e6f 100644 --- a/src/southbridge/intel/i82870/82870.h +++ b/src/southbridge/intel/i82870/82870.h @@ -16,9 +16,9 @@ #define ABAR 0x40 /* for pci bridge 1460 */ -#define MTT 0x042 -#define HCCR 0x0f0 -#define ACNF 0x0e0 +#define MTT 0x042 +#define HCCR 0x0f0 +#define ACNF 0x0e0 #define STRP 0x44 // Strap status register #define STRP_EN133 0x0001 // 133 MHz-capable (Px_133EN) |