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author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-23 21:47:45 +0100 |
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committer | Nico Huber <nico.h@gmx.de> | 2018-05-25 20:32:58 +0000 |
commit | e8620146d964df8e5adfb084ed503bef2d877321 (patch) | |
tree | d742e5f691348f8e4304d77c991657dc7c409988 /src/southbridge/intel/i82870/pcibridge.c | |
parent | 59326f35a98beca19b6aeb5c1c95ca1a1f7d8e76 (diff) |
sb/intel/common/pirq_gen: Rework generating pin-route tables
This creates a pin-route matrix first and then generates the ACPI
entries based on that. This approach has the advantage of being
simpler (no need for checks on double entries) and requiring less
access to the pci config space.
A few thing that are also fixed:
* Don't declare DEFAULT_RCBA redundantly.
* Only loop over PCI devices on bus 0
* Add a license header to rcba_pirq.c
* Remove inappropriate use of typedefs
* Fix the pin field: needs to be a byte
* Fix the source field: it should either be a byte or a path
(according to Advanced Configuration and Power Interface Specification
rev 2.0c)
Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22979
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82870/pcibridge.c')
0 files changed, 0 insertions, 0 deletions