summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801xx
diff options
context:
space:
mode:
authorJoseph Smith <joe@smittys.pointclark.net>2008-04-06 04:26:19 +0000
committerJoseph Smith <joe@smittys.pointclark.net>2008-04-06 04:26:19 +0000
commit0dc5697220773719cd18e23c795c55f864f03a1d (patch)
treef7d8c73d8331967201d54af8a2ff90aa73da1d42 /src/southbridge/intel/i82801xx
parent3860404b651d7c92c86a9789f9c163efb7ec9c8a (diff)
This patch halts the tco timer early in the boot process on all ICH series southbridges.
It also keeps the boot processes from rebooting through out the coreboot process. Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801xx')
-rw-r--r--src/southbridge/intel/i82801xx/i82801xx.h4
-rw-r--r--src/southbridge/intel/i82801xx/i82801xx_early_lpc.c40
-rw-r--r--src/southbridge/intel/i82801xx/i82801xx_lpc.c1
3 files changed, 44 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801xx/i82801xx.h b/src/southbridge/intel/i82801xx/i82801xx.h
index e5b2d33ba4..27ce21c207 100644
--- a/src/southbridge/intel/i82801xx/i82801xx.h
+++ b/src/southbridge/intel/i82801xx/i82801xx.h
@@ -34,6 +34,7 @@ extern void i82801xx_enable(device_t dev);
#define GEN_PMCON_3 0xa4
#define PMBASE 0x40
+#define PMBASE_ADDR 0x0400 /* ACPI Base Address Register */
#define ACPI_CNTL 0x44
#define BIOS_CNTL 0x4E
#define GPIO_BASE_ICH0_5 0x58 /* LPC GPIO Base Addr. Reg. (ICH0-ICH5) */
@@ -68,6 +69,9 @@ extern void i82801xx_enable(device_t dev);
#define MTT 0x70
#define PCI_MAST_STS 0x82
+#define TCOBASE 0x60 /* TCO Base Address Register */
+#define TCO1_CNT 0x08 /* TCO1 Control Register */
+
/* GEN_PMCON_3 bits */
#define RTC_BATTERY_DEAD (1 << 2)
#define RTC_POWER_FAILED (1 << 1)
diff --git a/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c b/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
new file mode 100644
index 0000000000..21b8fc2893
--- /dev/null
+++ b/src/southbridge/intel/i82801xx/i82801xx_early_lpc.c
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+static void i82801xx_halt_tco_timer(void)
+{
+ device_t dev;
+ uint16_t halt_tco_timer;
+
+ /* Set the LPC device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x0);
+
+ /* Temporarily set ACPI base address (I/O space). */
+ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));
+
+ /* Temporarily enable ACPI I/O. */
+ pci_write_config8(dev, ACPI_CNTL, 0x10);
+
+ /* Halt the TCO timer, preventing SMI and automatic reboot */
+ outw(inw(PMBASE_ADDR + TCOBASE + TCO1_CNT) | (1 << 11), PMBASE_ADDR + TCOBASE + TCO1_CNT);
+
+ /* Disable ACPI I/O. */
+ pci_write_config8(dev, ACPI_CNTL, 0x00);
+}
diff --git a/src/southbridge/intel/i82801xx/i82801xx_lpc.c b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
index 096be1a67e..17d4819c62 100644
--- a/src/southbridge/intel/i82801xx/i82801xx_lpc.c
+++ b/src/southbridge/intel/i82801xx/i82801xx_lpc.c
@@ -32,7 +32,6 @@
#include <arch/io.h>
#include "i82801xx.h"
-#define PMBASE_ADDR 0x00000400 /* ACPI Base Address Register */
#define GPIO_BASE_ADDR 0x00000500 /* GPIO Base Address Register */
#define NMI_OFF 0