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authorKyösti Mälkki <kyosti.malkki@gmail.com>2021-01-29 23:14:53 +0200
committerKyösti Mälkki <kyosti.malkki@gmail.com>2021-02-06 07:16:16 +0000
commit8fee9951d30d03b4bca16c198b887c5415418c12 (patch)
tree929be61cb85aee7c83bcc4e91f82ef379e960b60 /src/southbridge/intel/i82801jx
parent68d68f1d7c7693f7e49634b6c2106d3c2630d4b0 (diff)
sb,soc/intel: Add wake source fields in GNVS
For the moment, these are most not used but become a necessity for a unified <soc/nvs.h> approach. They would be required for the implementation of _SWS method for OSPM to determine the reason for system waking up. The related hardware registers are present with these platforms. It's expected that ACPI power-management related GNVS entries are grouped together to form a single struct in later works. Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
-rw-r--r--src/southbridge/intel/i82801jx/acpi/globalnvs.asl2
-rw-r--r--src/southbridge/intel/i82801jx/include/soc/nvs.h4
2 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
index d2af885b0e..264b52a3b0 100644
--- a/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
+++ b/src/southbridge/intel/i82801jx/acpi/globalnvs.asl
@@ -103,4 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
DOCK, 8, // 0xf0 - Docking Status
BTEN, 8, // 0xf1 - Bluetooth Enable
CBMC, 32,
+ PM1I, 32, // System Wake Source - PM1 Index
+ GPEI, 32, // GPE Wake Source
}
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h
index 4325a8c1ee..54c4a2c7c4 100644
--- a/src/southbridge/intel/i82801jx/include/soc/nvs.h
+++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h
@@ -97,6 +97,10 @@ struct __packed global_nvs {
u8 bten;
u32 cbmc;
+
+ /* Required for future unified acpi_save_wake_source. */
+ u32 pm1i;
+ u32 gpei;
};
#endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */