diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-19 16:19:44 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-18 18:02:27 +0000 |
| commit | 66c6413c69abb7335efc4ea07f4c811c042704b6 (patch) | |
| tree | 06d58b85da4c779cca7b78e33a069ea03a4e69e4 /src/southbridge/intel/i82801jx | |
| parent | c4a6628a6fe4f5400b7abe1478d0b0b21cb8200f (diff) | |
ACPI: Refactor ChromeOS specific ACPI GNVS
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx')
| -rw-r--r-- | src/southbridge/intel/i82801jx/include/soc/nvs.h | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801jx/include/soc/nvs.h b/src/southbridge/intel/i82801jx/include/soc/nvs.h index 96c0a40e05..d2de581aa7 100644 --- a/src/southbridge/intel/i82801jx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801jx/include/soc/nvs.h @@ -97,7 +97,6 @@ struct __packed global_nvs { u8 bten; u32 cbmc; - u8 rsvd13[10]; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */ |