diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2017-07-21 10:06:17 +0530 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-07-21 14:45:31 +0000 |
| commit | 8e39009c57dc92e6970a812ec82a2cee4cb6ced5 (patch) | |
| tree | 533d7e13c88b394db384d806af8f22c80105c6a6 /src/southbridge/intel/i82801jx/thermal.c | |
| parent | ba3ae3eead28d1fbae0527abca091a01b6876cb6 (diff) | |
common/block/fast_spi: Perform SPI offset read after lock down operation
This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/thermal.c')
0 files changed, 0 insertions, 0 deletions