diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/thermal.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/thermal.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/thermal.c | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 70a98388a9..41013a3596 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -14,11 +14,9 @@ static void thermal_init(struct device *dev) return; u8 reg8; - u32 reg32; pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); - reg32 = pci_read_config32(dev, 0x04); - pci_write_config32(dev, 0x04, reg32 | (1 << 1)); + pci_or_config32(dev, 0x04, 1 << 1); write32(DEFAULT_TBAR + 0x04, 0); /* Clear thermal trip points. */ write32(DEFAULT_TBAR + 0x44, 0); @@ -31,8 +29,7 @@ static void thermal_init(struct device *dev) reg8 = read8(DEFAULT_TBAR + 0x48); write8(DEFAULT_TBAR + 0x48, reg8 | (1 << 7)); - reg32 = pci_read_config32(dev, 0x04); - pci_write_config32(dev, 0x04, reg32 & ~(1 << 1)); + pci_and_config32(dev, 0x04, ~(1 << 1)); pci_write_config32(dev, 0x10, 0); } |