diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/pci.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/pci.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/pci.c | 8 |
1 files changed, 2 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801jx/pci.c b/src/southbridge/intel/i82801jx/pci.c index 020ecdeafb..36769d0eee 100644 --- a/src/southbridge/intel/i82801jx/pci.c +++ b/src/southbridge/intel/i82801jx/pci.c @@ -9,18 +9,14 @@ static void pci_init(struct device *dev) { u16 reg16; - u8 reg8; /* This device has no interrupt */ pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); /* Master Latency Count must be set to 0x04! */ - reg8 = pci_read_config8(dev, D30F0_SMLT); - reg8 &= 0x07; - reg8 |= (0x04 << 3); - pci_write_config8(dev, D30F0_SMLT, reg8); + pci_update_config8(dev, D30F0_SMLT, 0x07, 0x04 << 3); - /* Clear errors in status registers */ + /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, PCI_STATUS); //reg16 |= 0xf900; pci_write_config16(dev, PCI_STATUS, reg16); |