diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/lpc.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 18 |
1 files changed, 6 insertions, 12 deletions
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index 3be492df21..a590aec154 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -160,8 +160,7 @@ static void i82801jx_power_options(struct device *dev) int nmi_option; /* BIOS must program... */ - reg32 = pci_read_config32(dev, 0xac); - pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8)); + pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8)); /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On @@ -281,18 +280,13 @@ static void i82801jx_power_options(struct device *dev) static void i82801jx_configure_cstates(struct device *dev) { - u8 reg8; - - reg8 = pci_read_config8(dev, D31F0_CxSTATE_CNF); - reg8 |= (1 << 4) | (1 << 3) | (1 << 2); // Enable Popup & Popdown - pci_write_config8(dev, D31F0_CxSTATE_CNF, reg8); + // Enable Popup & Popdown + pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2)); // Set Deeper Sleep configuration to recommended values - reg8 = pci_read_config8(dev, D31F0_C4TIMING_CNT); - reg8 &= 0xf0; - reg8 |= (2 << 2); // Deeper Sleep to Stop CPU: 34-40us - reg8 |= (2 << 0); // Deeper Sleep to Sleep: 15us - pci_write_config8(dev, D31F0_C4TIMING_CNT, reg8); + // Deeper Sleep to Stop CPU: 34-40us + // Deeper Sleep to Sleep: 15us + pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0)); /* We could enable slow-C4 exit here, if someone needs it? */ } |