diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 13:36:44 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-05-24 18:05:56 +0000 |
| commit | 1a8c1df55bf7bd84a16ac49f420001d66292dd87 (patch) | |
| tree | c03118bc61fa12f87f91f9b92590b3f561e1d972 /src/southbridge/intel/i82801jx/lpc.c | |
| parent | ac350f82cd4dfab20a6fb49e5dea536ae448e054 (diff) | |
sb/intel/i82801jx: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: I37be7672c88b28180d7d4b46928ebed8472ec020
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801jx/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/lpc.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index c631da9394..ff86f0fddd 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -91,9 +91,9 @@ static void i82801jx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801jx_pirq_init(device_t dev) +static void i82801jx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Interrupt 11 is not used by legacy devices and so can always be used * for PCI interrupts. Full legacy IRQ routing is complicated and hard @@ -134,7 +134,7 @@ static void i82801jx_pirq_init(device_t dev) } } -static void i82801jx_gpi_routing(device_t dev) +static void i82801jx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801jx_gpi_routing(device_t dev) pci_write_config32(dev, D31F0_GPIO_ROUT, reg32); } -static void i82801jx_power_options(device_t dev) +static void i82801jx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -295,7 +295,7 @@ static void i82801jx_power_options(device_t dev) outl(reg32, pmbase + 0x10); } -static void i82801jx_configure_cstates(device_t dev) +static void i82801jx_configure_cstates(struct device *dev) { u8 reg8; @@ -501,7 +501,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -616,7 +616,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } -static void i82801jx_lpc_read_resources(device_t dev) +static void i82801jx_lpc_read_resources(struct device *dev) { int i, io_index = 0; /* @@ -687,7 +687,7 @@ static void i82801jx_lpc_read_resources(device_t dev) } } -static void set_subsystem(device_t dev, unsigned vendor, unsigned device) +static void set_subsystem(struct device *dev, unsigned vendor, unsigned device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -698,7 +698,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); @@ -720,9 +720,9 @@ static void southbridge_inject_dsdt(device_t dev) } } -static void southbridge_fill_ssdt(device_t device) +static void southbridge_fill_ssdt(struct device *device) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); |