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author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-18 16:33:39 +0300 |
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committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-08-21 07:00:45 +0000 |
commit | 12b121cdb450d96309dd96b2ccc25fc5501d2250 (patch) | |
tree | 1d94c123c23512b811d69d9876ac9a860bbbe0f6 /src/southbridge/intel/i82801jx/i82801jx.h | |
parent | 544b572c07bb09aba36705b5d8ffca3b793323f6 (diff) |
southbridge/intel: Tidy up preprocessor and headers
Change-Id: I52a7b39566acd64ac21a345046675e05649a40f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34980
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/i82801jx.h')
-rw-r--r-- | src/southbridge/intel/i82801jx/i82801jx.h | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 80d6cbd04f..28c9f68ea2 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -18,12 +18,6 @@ #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H #define SOUTHBRIDGE_INTEL_I82801GX_I82801JX_H -#ifndef __ACPI__ -#ifndef __ASSEMBLER__ -#include "chip.h" -#endif -#endif - #define DEFAULT_TBAR ((u8 *)0xfed1b000) #include <southbridge/intel/common/rcba.h> @@ -222,7 +216,6 @@ #ifndef __ACPI__ -#ifndef __ASSEMBLER__ #include <device/pci_ops.h> @@ -232,7 +225,7 @@ static inline int lpc_is_mobile(const u16 devid) } #define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) -#if defined(__PRE_RAM__) +#if ENV_ROMSTAGE void enable_smbus(void); int smbus_read_byte(unsigned device, unsigned address); int i2c_eeprom_read(unsigned int device, unsigned int cmd, unsigned int bytes, @@ -243,6 +236,5 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #endif #endif -#endif #endif |