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authorArthur Heymans <arthur@aheymans.xyz>2017-04-09 20:40:39 +0200
committerMartin Roth <martinroth@google.com>2017-07-21 15:43:18 +0000
commit7b9c139ac26eded525980e896b354c99c08cdca7 (patch)
treea30eb4f79395626495a106b7ca1f138753c90636 /src/southbridge/intel/i82801jx/early_smbus.c
parentc3198543b690fbdeda0f1e1ffaf78048fe765ec0 (diff)
sb/intel/i82801jx: Copy i82801ix
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/early_smbus.c')
-rw-r--r--src/southbridge/intel/i82801jx/early_smbus.c58
1 files changed, 58 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/early_smbus.c b/src/southbridge/intel/i82801jx/early_smbus.c
new file mode 100644
index 0000000000..31b33e92d9
--- /dev/null
+++ b/src/southbridge/intel/i82801jx/early_smbus.c
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <device/pci_ids.h>
+#include <device/pci_def.h>
+#include "i82801ix.h"
+#include "smbus.h"
+
+void enable_smbus(void)
+{
+ pci_devfn_t dev;
+
+ /* Set the SMBus device statically. */
+ dev = PCI_DEV(0x0, 0x1f, 0x3);
+
+ /* Check to make sure we've got the right device. */
+ if (pci_read_config16(dev, 0x2) != 0x2930) {
+ die("SMBus controller not found!");
+ }
+
+ /* Set SMBus I/O base. */
+ pci_write_config32(dev, SMB_BASE,
+ SMBUS_IO_BASE | PCI_BASE_ADDRESS_SPACE_IO);
+
+ /* Set SMBus enable. */
+ pci_write_config8(dev, HOSTC, HST_EN);
+
+ /* Set SMBus I/O space enable. */
+ pci_write_config16(dev, PCI_COMMAND, PCI_COMMAND_IO);
+
+ /* Disable interrupt generation. */
+ outb(0, SMBUS_IO_BASE + SMBHSTCTL);
+
+ /* Clear any lingering errors, so transactions can run. */
+ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
+ printk(BIOS_DEBUG, "SMBus controller enabled.\n");
+}
+
+int smbus_read_byte(unsigned device, unsigned address)
+{
+ return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
+}