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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-01-04 14:23:54 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-09 09:56:06 +0000 |
| commit | 4513020064cc4765e723f6f3cc2b8a45a0dc6545 (patch) | |
| tree | e9b31b8b64518a62f6a7885a1de54171471c918b /src/southbridge/intel/i82801jx/early_lpc.c | |
| parent | 907bd5d44e574227baa1f5b3c00b31b8dc351096 (diff) | |
cpu/intel: Use the common code to initialize the romstage timestamps
The initial timestamps are now pushed on the stack when entering the
romstage C code.
Tested on Asus P5QC.
Change-Id: I88e972caafff5c53d8e68e85415f920c7341b92d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/early_lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/early_lpc.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/src/southbridge/intel/i82801jx/early_lpc.c b/src/southbridge/intel/i82801jx/early_lpc.c index 74f0ee2920..a59fdccedc 100644 --- a/src/southbridge/intel/i82801jx/early_lpc.c +++ b/src/southbridge/intel/i82801jx/early_lpc.c @@ -15,21 +15,10 @@ */ #include <arch/io.h> -#include <timestamp.h> -#include <cpu/x86/tsc.h> #include <console/console.h> #include <arch/acpi.h> #include "i82801jx.h" -uint64_t get_initial_timestamp(void) -{ - tsc_t base_time = { - .lo = pci_read_config32(PCI_DEV(0, 0x00, 0), 0xdc), - .hi = pci_read_config32(PCI_DEV(0, 0x1f, 2), 0xd0) - }; - return tsc_to_uint64(base_time); -} - int southbridge_detect_s3_resume(void) { u32 reg32; |