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authorArthur Heymans <arthur@aheymans.xyz>2017-04-09 20:40:39 +0200
committerMartin Roth <martinroth@google.com>2017-07-21 15:43:18 +0000
commit7b9c139ac26eded525980e896b354c99c08cdca7 (patch)
treea30eb4f79395626495a106b7ca1f138753c90636 /src/southbridge/intel/i82801jx/chip.h
parentc3198543b690fbdeda0f1e1ffaf78048fe765ec0 (diff)
sb/intel/i82801jx: Copy i82801ix
Change-Id: I878960e7e0f992426382ca717b8b42787f01ebc6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/chip.h')
-rw-r--r--src/southbridge/intel/i82801jx/chip.h91
1 files changed, 91 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h
new file mode 100644
index 0000000000..307b751fab
--- /dev/null
+++ b/src/southbridge/intel/i82801jx/chip.h
@@ -0,0 +1,91 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ * 2012 secunet Security Networks AG
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
+#define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
+
+enum {
+ THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3,
+ THTL_50_0 = 4, THTL_37_5 = 5, THTL_25_0 = 6, THTL_12_5 = 7
+};
+
+struct southbridge_intel_i82801ix_config {
+ /**
+ * Interrupt Routing configuration
+ * If bit7 is 1, the interrupt is disabled.
+ */
+ uint8_t pirqa_routing;
+ uint8_t pirqb_routing;
+ uint8_t pirqc_routing;
+ uint8_t pirqd_routing;
+ uint8_t pirqe_routing;
+ uint8_t pirqf_routing;
+ uint8_t pirqg_routing;
+ uint8_t pirqh_routing;
+
+ /**
+ * GPI Routing configuration
+ *
+ * Only the lower two bits have a meaning:
+ * 00: No effect
+ * 01: SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
+ * 10: SCI (if corresponding GPIO_EN bit is also set)
+ * 11: reserved
+ */
+ uint8_t gpi0_routing;
+ uint8_t gpi1_routing;
+ uint8_t gpi2_routing;
+ uint8_t gpi3_routing;
+ uint8_t gpi4_routing;
+ uint8_t gpi5_routing;
+ uint8_t gpi6_routing;
+ uint8_t gpi7_routing;
+ uint8_t gpi8_routing;
+ uint8_t gpi9_routing;
+ uint8_t gpi10_routing;
+ uint8_t gpi11_routing;
+ uint8_t gpi12_routing;
+ uint8_t gpi13_routing;
+ uint8_t gpi14_routing;
+ uint8_t gpi15_routing;
+
+ uint32_t gpe0_en;
+ uint16_t alt_gp_smi_en;
+
+ /* IDE configuration */
+ uint8_t sata_port_map : 6;
+ int sata_clock_request : 1;
+ int sata_traffic_monitor : 1;
+
+ int c4onc3_enable:1;
+ int c5_enable : 1;
+ int c6_enable : 1;
+
+ int throttle_duty : 3;
+
+ /* Bit mask to tell whether a PCIe slot is implemented as slot. */
+ int pcie_slot_implemented : 6;
+
+ /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */
+ struct {
+ uint8_t value : 8;
+ uint8_t scale : 2;
+ } pcie_power_limits[6];
+
+ uint8_t pcie_hotplug_map[8];
+};
+
+#endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */