diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2022-02-18 14:21:45 +0100 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-03-25 20:00:49 +0000 |
| commit | 7e397ac4e7601b1e20653b86f95c57e7acc0c713 (patch) | |
| tree | 8790283ff5d70bbca91f429b97fa75deb0b66f3e /src/southbridge/intel/i82801jx/chip.h | |
| parent | cdad992f0f3230bf27150290c47ecf72d20c121b (diff) | |
sb/intel/i82801i/jx/chip.h: Use unsigned ints for bitfields
Clang complains about this.
Change-Id: I3d6c333bb884ebc0ae50c4437f2cd98e74cf7379
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Diffstat (limited to 'src/southbridge/intel/i82801jx/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801jx/chip.h | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index e9632d25de..ae31d4f224 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -42,16 +42,16 @@ struct southbridge_intel_i82801jx_config { /* IDE configuration */ uint8_t sata_port_map : 6; - int sata_clock_request : 1; + unsigned int sata_clock_request : 1; - int c4onc3_enable:1; - int c5_enable : 1; - int c6_enable : 1; + unsigned int c4onc3_enable:1; + unsigned int c5_enable : 1; + unsigned int c6_enable : 1; - int throttle_duty : 3; + unsigned int throttle_duty : 3; /* Bit mask to tell whether a PCIe slot is implemented as slot. */ - int pcie_slot_implemented : 6; + unsigned int pcie_slot_implemented : 6; /* Power limits for PCIe ports. Values are in 10^(-scale) watts. */ struct { |