diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:29:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:23:07 +0000 |
| commit | c484da1a98610d783131a3a3998c0a999b97f9f5 (patch) | |
| tree | c4e25f9b4fbde15a9962b9d0c7d7117997e26ad1 /src/southbridge/intel/i82801jx/chip.h | |
| parent | fecf77770b8e68b9ef82021ca53c31db93736d93 (diff) | |
sb/intel/i82801jx: Add common code for LPC decode
Change-Id: Id706da33f06ceeec39ea50301130770226f0474e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801jx/chip.h')
| -rw-r--r-- | src/southbridge/intel/i82801jx/chip.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index 1712b8162c..e4c68fb95a 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -78,6 +78,12 @@ struct southbridge_intel_i82801jx_config { } pcie_power_limits[6]; uint8_t pcie_hotplug_map[8]; + + /* Additional LPC IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; }; #endif /* SOUTHBRIDGE_INTEL_I82801JX_CHIP_H */ |