diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 02:09:33 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 00:12:17 +0000 |
| commit | 2048cb43863f014fedc4ff44233d49410f0cee5e (patch) | |
| tree | 1be140c2bf5bd48f278039d1c32d5fa382379a86 /src/southbridge/intel/i82801jx/bootblock.c | |
| parent | efd23d92efb982f74b8473201bc93b1c0ad64bc8 (diff) | |
sb/intel/i82801jx: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801jx/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801jx/bootblock.c | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index e38848fe0c..74cf80ed51 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -6,15 +6,7 @@ static void enable_spi_prefetch(void) { - u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); - - reg8 = pci_read_config8(dev, 0xdc); - reg8 &= ~(3 << 2); - reg8 |= (2 << 2); /* Prefetching and Caching Enabled */ - pci_write_config8(dev, 0xdc, reg8); + pci_update_config8(PCI_DEV(0, 0x1f, 0), 0xdc, ~(3 << 2), 2 << 2); } void bootblock_early_southbridge_init(void) |