diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2020-12-29 05:12:56 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-20 09:24:35 +0000 |
| commit | 780e02d1a54598f60f290e7eaba3c0456006ecce (patch) | |
| tree | 334397f52b6f0d3edf300eb1fcf8c15415631ed5 /src/southbridge/intel/i82801ix | |
| parent | c196246f75ae8fd235055250593fc7a78f5f3888 (diff) | |
ACPI GNVS: Drop APIC, factor out MPEN
APIC was not referenced anywhere in ASL.
MPEN has references under boards:
getac/p470, roda/rk9, roda/rk886ex.
MPEN has reference also in Intel SpeedStep ASL.
Replace static MPEN with detection of multiple CPUs
installed.
Change-Id: Ib5f06416b23196b7227ccd5814162925c31c084b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/include/soc/nvs.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/lpc.c | 8 |
3 files changed, 10 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index 5687eb0e0b..021de14e2c 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -53,7 +53,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) B2SS, 8, // 0x24 - BAT2 stored status /* Processor Identification */ Offset (0x28), - APIC, 8, // 0x28 - APIC Enabled by coreboot + , 8, // 0x28 - Enabled by coreboot MPEN, 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 diff --git a/src/southbridge/intel/i82801ix/include/soc/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h index e8150dcc86..4fa56763bc 100644 --- a/src/southbridge/intel/i82801ix/include/soc/nvs.h +++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h @@ -40,7 +40,7 @@ struct __packed global_nvs { u8 b0ss, b1ss, b2ss; /* 0x22-0x24 - stored status */ u8 rsvd3[3]; /* Processor Identification */ - u8 apic; /* 0x28 - APIC enabled */ + u8 unused_was_apic; /* 0x28 - APIC enabled */ u8 mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index b84b458027..5400237fa8 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -12,6 +12,7 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> +#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <string.h> @@ -20,6 +21,7 @@ #include <southbridge/intel/common/pciehp.h> #include <southbridge/intel/common/pmutil.h> #include <southbridge/intel/common/acpi_pirq_gen.h> +#include <soc/nvs.h> #define NMI_OFF 0 @@ -450,6 +452,12 @@ static void i82801ix_lpc_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +void soc_fill_gnvs(struct global_nvs *gnvs) +{ + /* MPEN, Enable Multi Processing. */ + gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; +} + static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; |