diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-08-19 21:40:21 +0200 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2020-09-21 16:29:35 +0000 |
| commit | 131d9f5190a1e5b6fd5a47fecbe5f7eef002c0ef (patch) | |
| tree | accfc86126dba3bf22fe731689ee791894a3bcaa /src/southbridge/intel/i82801ix | |
| parent | b69bbfe1ef52421f0bbe1e632d99dc264660ee02 (diff) | |
src/southbridge: Drop unneeded empty lines
Change-Id: I02aa1e2a9a9061b34b91f832d96123a8595d61b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix')
| -rw-r--r-- | src/southbridge/intel/i82801ix/dmi_setup.c | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.h | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/smi.c | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/smihandler.c | 1 |
4 files changed, 0 insertions, 12 deletions
diff --git a/src/southbridge/intel/i82801ix/dmi_setup.c b/src/southbridge/intel/i82801ix/dmi_setup.c index ffc57f2e1a..cbb52c4a6c 100644 --- a/src/southbridge/intel/i82801ix/dmi_setup.c +++ b/src/southbridge/intel/i82801ix/dmi_setup.c @@ -38,7 +38,6 @@ void i82801ix_dmi_setup(void) RCBA8(RCBA_BCR) = 0x45; RCBA32(RCBA_CIR6) &= ~(1 << 7); - /* VC1 setup for isochronous transfers: */ /* Set VC1 virtual channel id to 1. */ @@ -60,7 +59,6 @@ void i82801ix_dmi_setup(void) /* Enable VC1. */ RCBA32(RCBA_V1CTL) |= (1 << 31); - /* Setup RCRB: */ /* Set component id to 2 for southbridge, northbridge has id 1. */ diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 3bd1d49869..56f14b0d2f 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -20,11 +20,8 @@ #define DEFAULT_TCOBASE (DEFAULT_PMBASE + 0x60) #define DEFAULT_GPIOBASE 0x00000580 - #define APM_CNT 0xb2 - - #define GP_IO_USE_SEL 0x00 #define GP_IO_SEL 0x04 #define GP_LVL 0x0c @@ -73,23 +70,19 @@ #define D31F0_CxSTATE_CNF 0xa9 #define D31F0_C4TIMING_CNT 0xaa - /* D31:F2 SATA */ #define D31F2_IDE_TIM_PRI 0x40 #define D31F2_IDE_TIM_SEC 0x42 #define D31F2_SIDX 0xa0 #define D31F2_SDAT 0xa4 - /* D30:F0 PCI-to-PCI bridge */ #define D30F0_SMLT 0x1b - /* D28:F0-5 PCIe root ports */ #define D28Fx_XCAP 0x42 #define D28Fx_SLCAP 0x54 - /* PCI Configuration Space (D31:F3): SMBus */ #define SMB_BASE 0x20 #define HOSTC 0x40 @@ -154,7 +147,6 @@ #define FD_SD (1 << 3) /* SMBus */ #define FD_SAD1 (1 << 2) /* SATA #1 */ - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index 4f47e34142..1abd8c5a55 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -114,7 +114,6 @@ static void aseg_smm_install(void) return; smm_handler_copied = 1; - /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c index 699f51f712..537e544f94 100644 --- a/src/southbridge/intel/i82801ix/smihandler.c +++ b/src/southbridge/intel/i82801ix/smihandler.c @@ -51,7 +51,6 @@ void southbridge_smi_monitor(void) mask |= (0xff << ((i - 16) << 3)); } - /* IOTRAP(3) SMI function call */ if (IOTRAP(3)) { if (gnvs && gnvs->smif) |