ACPI: Select ACPI_SOC_NVS only where suitable

Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.

Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.

Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao

5 files changed, 4 insertions, 14 deletions

diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig
index be640db0c3..3ee2943090 100644
--- a/src/southbridge/intel/i82801ix/Kconfig
+++ b/src/southbridge/intel/i82801ix/Kconfig
@@ -3,6 +3,7 @@
 config SOUTHBRIDGE_INTEL_I82801IX
 	bool
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select ACPI_SOC_NVS
 	select AZALIA_PLUGIN_SUPPORT
 	select HAVE_SMI_HANDLER if !NO_SMM
 	select HAVE_USBDEBUG_OPTIONS
diff --git a/src/southbridge/intel/i82801ix/Makefile.inc b/src/southbridge/intel/i82801ix/Makefile.inc
index 516a344e62..8eabd49300 100644
--- a/src/southbridge/intel/i82801ix/Makefile.inc
+++ b/src/southbridge/intel/i82801ix/Makefile.inc
@@ -29,4 +29,6 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/smm/smmrelocate.S
 endif
 
+CPPFLAGS_common += -I$(src)/southbridge/intel/i82801ix/include
+
 endif
diff --git a/src/southbridge/intel/i82801ix/nvs.h b/src/southbridge/intel/i82801ix/include/soc/nvs.h
index 83dd7e508d..83dd7e508d 100644
--- a/src/southbridge/intel/i82801ix/nvs.h
+++ b/src/southbridge/intel/i82801ix/include/soc/nvs.h
diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c
index 0b58e67425..b84b458027 100644
--- a/src/southbridge/intel/i82801ix/lpc.c
+++ b/src/southbridge/intel/i82801ix/lpc.c
@@ -12,13 +12,11 @@
 #include <device/pci_ops.h>
 #include <arch/ioapic.h>
 #include <acpi/acpi.h>
-#include <acpi/acpi_gnvs.h>
 #include <cpu/x86/smm.h>
 #include <acpi/acpigen.h>
 #include <string.h>
 #include "chip.h"
 #include "i82801ix.h"
-#include "nvs.h"
 #include <southbridge/intel/common/pciehp.h>
 #include <southbridge/intel/common/pmutil.h>
 #include <southbridge/intel/common/acpi_pirq_gen.h>
@@ -452,17 +450,6 @@ static void i82801ix_lpc_read_resources(struct device *dev)
 	res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 }
 
-size_t gnvs_size_of_array(void)
-{
-	return sizeof(struct global_nvs);
-}
-
-/* To build emulation/qemu-q35 with CHROMEOS. */
-void *gnvs_chromeos_ptr(struct global_nvs *gnvs)
-{
-	return 0;
-}
-
 static const char *lpc_acpi_name(const struct device *dev)
 {
 	return "LPCB";
diff --git a/src/southbridge/intel/i82801ix/smihandler.c b/src/southbridge/intel/i82801ix/smihandler.c
index 046cc2b5d5..0483447e94 100644
--- a/src/southbridge/intel/i82801ix/smihandler.c
+++ b/src/southbridge/intel/i82801ix/smihandler.c
@@ -7,7 +7,7 @@
 #include <southbridge/intel/common/pmutil.h>
 #include "i82801ix.h"
 
-#include "nvs.h"
+#include <soc/nvs.h>
 
 #if !CONFIG(SMM_TSEG)
 /* For qemu/x86-q35 to build properly. */