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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:35:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:20:34 +0200 |
| commit | 9b143e1474f425b6d81bf6490d67baf26d03c437 (patch) | |
| tree | a741e62aab6d51d33ddc74046233948f8841c441 /src/southbridge/intel/i82801ix/pcie.c | |
| parent | 35a7249183d2e791eb00b41332e6277c504cdd49 (diff) | |
intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/pcie.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/pcie.c | 14 |
1 files changed, 5 insertions, 9 deletions
diff --git a/src/southbridge/intel/i82801ix/pcie.c b/src/southbridge/intel/i82801ix/pcie.c index ce5d265de7..f53519d5fc 100644 --- a/src/southbridge/intel/i82801ix/pcie.c +++ b/src/southbridge/intel/i82801ix/pcie.c @@ -56,23 +56,19 @@ static void pci_init(struct device *dev) reg32 |= (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0); pci_write_config32(dev, 0xe1, reg32); -#if CONFIG_MMCONF_SUPPORT /* Set VC0 transaction class */ - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); /* Mask completion timeouts */ - reg32 = pci_mmio_read_config32(dev, 0x148); + reg32 = pci_read_config32(dev, 0x148); reg32 |= (1 << 14); - pci_mmio_write_config32(dev, 0x148, reg32); + pci_write_config32(dev, 0x148, reg32); /* Lock R/WO Correctable Error Mask. */ - pci_mmio_write_config32(dev, 0x154, pci_mmio_read_config32(dev, 0x154)); -#else -#error "MMIO needed for ICH9 PCIe" -#endif + pci_write_config32(dev, 0x154, pci_read_config32(dev, 0x154)); /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); |