diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 11:13:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 01:10:17 +0000 |
| commit | 6740647cfd2d8ff8840d1e2ab37b66ce14b19180 (patch) | |
| tree | d2486eca3a88ef1141aaeba3d0774df247483d83 /src/southbridge/intel/i82801ix/i82801ix.c | |
| parent | e36733bf849e781d6e86a7549f2c17d246e619ac (diff) | |
sb/intel/i82801ix: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix/i82801ix.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.c | 11 |
1 files changed, 3 insertions, 8 deletions
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index b2b55ce015..16d0520bf9 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -52,18 +52,14 @@ static void i82801ix_pcie_init(const config_t *const info) if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { for (i = 0; i < 6; ++i) { if (pciePort[i]->enabled) { - reg32 = pci_read_config32(pciePort[i], 0xe8); - reg32 |= 1; - pci_write_config32(pciePort[i], 0xe8, reg32); + pci_or_config32(pciePort[i], 0xe8, 1); } } } for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ - reg32 = pci_read_config32(pciePort[i], 0x300); - reg32 |= 0x3 << 16; - pci_write_config32(pciePort[i], 0x300, reg32); + pci_or_config32(pciePort[i], 0x300, 0x3 << 16); } /* Set slot implemented, slot number and slot power limits. */ @@ -90,8 +86,7 @@ static void i82801ix_pcie_init(const config_t *const info) /* Lock R/WO ASPM support bits. */ for (i = 0; i < 6; ++i) { - reg32 = pci_read_config32(pciePort[i], 0x4c); - pci_write_config32(pciePort[i], 0x4c, reg32); + pci_update_config32(pciePort[i], 0x4c, ~0, 0); } } |