diff options
| author | Stefan Tauner <stefan.tauner@gmx.at> | 2018-08-15 08:06:13 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-08-16 16:31:00 +0000 |
| commit | 97c8089430869c1e2016b805703adbb0b038ab2a (patch) | |
| tree | 7008406efba5a5808eddf9c51d405e5a3b1e3f4c /src/southbridge/intel/i82801ix/i82801ix.c | |
| parent | cc68034ee9dfafab9ce2ac90d53299559a306980 (diff) | |
sb/intel/i82801[ij]x: do not set Chipset Initialization Register (CIR) 5
The specification updates for ICH 9 & 10 require to leave the
register in its default state by reserving all of its bits.
Writing to it does not seem to make a difference anyway since
reading it afterwards does not reflect the write (tested on ICH10).
Therefore we should omit the writes but document this fact in the
code because it is easy to miss from the datasheet alone.
Change-Id: Iec0d79f926a826a80b90907f7861d0cb2ca30a5b
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/i82801ix.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/i82801ix.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 7e91ba11c6..797856ea78 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -46,7 +46,7 @@ static void i82801ix_early_settings(const config_t *const info) RCBA32(RCBA_CIR9) = (RCBA32(RCBA_CIR9) & ~(0x3 << 26)) | (0x2 << 26); RCBA32(RCBA_CIR7) = (RCBA32(RCBA_CIR7) & ~(0xf << 16)) | (0x5 << 16); RCBA32(RCBA_CIR13) = (RCBA32(RCBA_CIR13) & ~(0xf << 16)) | (0x5 << 16); - RCBA32(RCBA_CIR5) |= (1 << 0); + /* RCBA32(RCBA_CIR5) |= (1 << 0); cf. Specification Update */ RCBA32(RCBA_CIR10) |= (3 << 16); } |