diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-07-26 08:35:09 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2013-09-10 18:20:34 +0200 |
| commit | 9b143e1474f425b6d81bf6490d67baf26d03c437 (patch) | |
| tree | a741e62aab6d51d33ddc74046233948f8841c441 /src/southbridge/intel/i82801ix/hdaudio.c | |
| parent | 35a7249183d2e791eb00b41332e6277c504cdd49 (diff) | |
intel/i82801ix: remove explicit pcie config accesses
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Diffstat (limited to 'src/southbridge/intel/i82801ix/hdaudio.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/hdaudio.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/src/southbridge/intel/i82801ix/hdaudio.c b/src/southbridge/intel/i82801ix/hdaudio.c index 13923140dc..49a0d958e1 100644 --- a/src/southbridge/intel/i82801ix/hdaudio.c +++ b/src/southbridge/intel/i82801ix/hdaudio.c @@ -237,39 +237,35 @@ static void azalia_init(struct device *dev) u8 reg8; u32 reg32; -#if CONFIG_MMCONF_SUPPORT // ESD - reg32 = pci_mmio_read_config32(dev, 0x134); + reg32 = pci_read_config32(dev, 0x134); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x134, reg32); + pci_write_config32(dev, 0x134, reg32); // Link1 description - reg32 = pci_mmio_read_config32(dev, 0x140); + reg32 = pci_read_config32(dev, 0x140); reg32 &= 0xff00ffff; reg32 |= (2 << 16); - pci_mmio_write_config32(dev, 0x140, reg32); + pci_write_config32(dev, 0x140, reg32); // Port VC0 Resource Control Register - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= 0xffffff00; reg32 |= 1; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // VCi traffic class - reg8 = pci_mmio_read_config8(dev, 0x44); + reg8 = pci_read_config8(dev, 0x44); reg8 |= (7 << 0); // TC7 - pci_mmio_write_config8(dev, 0x44, reg8); + pci_write_config8(dev, 0x44, reg8); // VCi Resource Control - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); reg32 |= (1 << 24); // VCi ID reg32 |= (0x80 << 0); // VCi map - pci_mmio_write_config32(dev, 0x120, reg32); -#else -#error ICH9 Azalia required CONFIG_MMCONF_SUPPORT -#endif + pci_write_config32(dev, 0x120, reg32); /* Set Bus Master */ reg32 = pci_read_config32(dev, PCI_COMMAND); |