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authorNaresh Solanki <naresh.solanki@9elements.com>2023-10-06 14:35:58 +0200
committerShelley Chen <shchen@google.com>2023-12-26 16:51:44 +0000
commit93ffdee5ed1e6ffc2c2f16d0b53a95c2b8b8d57b (patch)
tree179845e2a212cd8679b23e7ed4bd8ab3dadf1cf8 /src/southbridge/intel/i82801ix/fadt.c
parent8ed0cd0acc788f37ebfd47980843f1f39efe2581 (diff)
soc/intel/xeon/spr: Enforce POR frequency setting
For RMT build, add kconfig option to enforce Plan Of Record restriction on DDR5 frequency & voltage settings. Change-Id: Ibfcaaf47fec3bd5d8a858309918b3af2f8d976e9 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix/fadt.c')
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