sb/intel/i82801ix: Add common code to set up LPC IO decode ranges

This does the following:
- Add gen[1-4]_dec options to the devicetree to set up generic LPC
  decode ranges in the southbridge code.
- Move setting up some default decode ranges to a common place. If
  somehow a board needs to override this behavior it can happen in the
  mb_setup_superio() hook (that will be renamed when moving to
  C_ENVIRONMENT_BOOTBLOCK).

Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 32 insertions, 0 deletions

diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c
index da124ff54f..51ce9e859e 100644
--- a/src/southbridge/intel/i82801ix/early_init.c
+++ b/src/southbridge/intel/i82801ix/early_init.c
@@ -17,6 +17,7 @@
 #include <arch/io.h>
 #include <device/pci_ops.h>
 #include "i82801ix.h"
+#include "chip.h"
 
 void i82801ix_early_init(void)
 {
@@ -58,3 +59,34 @@ void i82801ix_early_init(void)
 	/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
 	         before they get cleared. */
 }
+
+void i82801ix_lpc_decode(void)
+{
+	const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
+	const struct device *dev = pcidev_on_root(0x1f, 0);
+	const struct southbridge_intel_i82801ix_config *config = NULL;
+
+	/* Configure serial IRQs.*/
+	pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
+	/*
+	 * Enable some common LPC IO ranges:
+	 * - 0x2e/0x2f, 0x4e/0x4f often SuperIO
+	 * - 0x60/0x64, 0x62/0x66 often KBC/EC
+	 * - 0x3f0-0x3f5/0x3f7 FDD
+	 * - 0x378-0x37f and 0x778-0x77f LPT
+	 * - 0x2f8-0x2ff COMB
+	 * - 0x3f8-0x3ff COMA
+	 */
+	pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
+	pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f);
+
+	/* Set up generic decode ranges */
+	if (!dev || !dev->chip_info)
+		return;
+	config = dev->chip_info;
+
+	pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
+	pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
+	pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
+	pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
+}