diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-06-08 11:13:42 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2020-06-12 01:10:17 +0000 |
| commit | 6740647cfd2d8ff8840d1e2ab37b66ce14b19180 (patch) | |
| tree | d2486eca3a88ef1141aaeba3d0774df247483d83 /src/southbridge/intel/i82801ix/early_init.c | |
| parent | e36733bf849e781d6e86a7549f2c17d246e619ac (diff) | |
sb/intel/i82801ix: Use PCI bitwise ops
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix/early_init.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/early_init.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index db17e73de9..18fe38b122 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -24,8 +24,7 @@ void i82801ix_early_init(void) /* Set up GPIOBASE. */ pci_write_config32(d31f0, D31F0_GPIO_BASE, DEFAULT_GPIOBASE); /* Enable GPIO. */ - pci_write_config8(d31f0, D31F0_GPIO_CNTL, - pci_read_config8(d31f0, D31F0_GPIO_CNTL) | 0x10); + pci_or_config8(d31f0, D31F0_GPIO_CNTL, 0x10); /* Reset watchdog. */ outw(0x0008, DEFAULT_TCOBASE + 0x04); /* R/WC, clear TCO caused SMI. */ @@ -40,6 +39,8 @@ void i82801ix_early_init(void) and 0xe (required if ME is disabled but present), bit 31 locks it. The other bits are 'must write'. */ u8 reg8 = pci_read_config8(d31f0, 0xac); + + /* FIXME: It's a 8-bit variable!!! */ reg8 |= (1 << 31) | (1 << 30) | (1 << 20) | (3 << 8); pci_write_config8(d31f0, 0xac, reg8); |