diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-10-17 22:13:43 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-11-23 04:59:26 +0000 |
| commit | f1c8ede1a5bcf26f938b3f5a8cfefa8acd156505 (patch) | |
| tree | 8ca85c50eab6eb4f2fb79950273d4fffb2136169 /src/southbridge/intel/i82801ix/bootblock.c | |
| parent | a35ad0e6ee7826dc1f171291116f306099c99e72 (diff) | |
sb/intel/i82801ix: fetch initial timestamp in bootblock
TESTED on Thinkpad x200
Change-Id: I3cd286709f8734793dc6ae303215433eff29d25b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801ix/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801ix/bootblock.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801ix/bootblock.c b/src/southbridge/intel/i82801ix/bootblock.c index 6252712eba..bb025b0eae 100644 --- a/src/southbridge/intel/i82801ix/bootblock.c +++ b/src/southbridge/intel/i82801ix/bootblock.c @@ -14,6 +14,19 @@ */ #include <arch/io.h> +#include <cpu/x86/tsc.h> + +static void store_initial_timestamp(void) +{ + /* + * We have two 32bit scratchpad registers available: + * D0:F0 0xdc (SKPAD) + * D31:F2 0xd0 (SATA SP) + */ + tsc_t tsc = rdtsc(); + pci_write_config32(PCI_DEV(0, 0x00, 0), 0xdc, tsc.lo); + pci_write_config32(PCI_DEV(0, 0x1f, 2), 0xd0, tsc.hi); +} static void enable_spi_prefetch(void) { @@ -30,5 +43,6 @@ static void enable_spi_prefetch(void) static void bootblock_southbridge_init(void) { + store_initial_timestamp(); enable_spi_prefetch(); } |