diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-25 17:05:35 +0200 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-02-11 16:37:28 +0000 |
| commit | aa969e887af6c76c0d5e694a3a17e14ee13d27b2 (patch) | |
| tree | 5f1c4ace30add956f2ccabed909a142fb351e856 /src/southbridge/intel/i82801ix/acpi | |
| parent | f6f1215cdbbae04de8f84654d064b376395cf203 (diff) | |
ACPI: Move PICM declaration
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801ix/acpi')
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801ix/acpi/pci.asl | 2 |
2 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl index d6fefbe661..a565ec8745 100644 --- a/src/southbridge/intel/i82801ix/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801ix/acpi/globalnvs.asl @@ -2,8 +2,6 @@ /* Global Variables */ -Name(\PICM, 0) // IOAPIC/8259 - Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ diff --git a/src/southbridge/intel/i82801ix/acpi/pci.asl b/src/southbridge/intel/i82801ix/acpi/pci.asl index c9a87bc565..6a5bcae130 100644 --- a/src/southbridge/intel/i82801ix/acpi/pci.asl +++ b/src/southbridge/intel/i82801ix/acpi/pci.asl @@ -45,7 +45,7 @@ Device (PCIB) // TODO: How many slots, where? // PCI Interrupt Routing. - // If PICM is set, interrupts are routed over the i8259, otherwise + // If PICM is _not_ set, interrupts are routed over the i8259, otherwise // over the IOAPIC. (Really? If they're above 15 they need to be routed // fixed over the IOAPIC?) |