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authorRonak Kanabar <ronak.kanabar@intel.com>2020-02-27 19:40:32 +0530
committerPatrick Georgi <pgeorgi@google.com>2020-03-25 10:45:08 +0000
commitba5062d78b8f3453d918a9096f08bfe393fd5922 (patch)
tree52277b7b8f2c1eb0a8ef1fbe8b575276b131a145 /src/southbridge/intel/i82801gx
parent2e4bc06b49b413d7524d748cc1626b1737dfd7d1 (diff)
mb/intel/jasperlake_rvp: Add memory config for Jasper Lake RVP
Add memory initialization parameters for Jasper Lake RVP boards Jasper Lake RVP supports two variants, one with memory LPDDR4 and another with DDR4 Based on board id, mainboard will pass correct memory parameters to the fsp. BUG=None BRANCH=None TEST=Check compilation for Jasper Lake RVP and check memory training passes. Change-Id: Idc92363a2148990df16c2068c7986013d015f604 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39195 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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