diff options
| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-27 20:25:51 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:54:31 +0000 |
| commit | 0b7446a2694ef8ad8c480602a7aee9ad90810ac7 (patch) | |
| tree | 8a3b558010219a6f6844dcb652d581f26f2bae4e /src/southbridge/intel/i82801gx | |
| parent | da321d883468f1306dc6105d3d924b12cb43fa06 (diff) | |
sb/intel/i82801gx,ix: Drop MPEN from GNVS
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/include/soc/nvs.h | 2 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 8 |
3 files changed, 2 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index dfd5a560c8..1e3889b4f5 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -45,7 +45,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Processor Identification */ Offset (0x28), , 8, // 0x28 - Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state diff --git a/src/southbridge/intel/i82801gx/include/soc/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h index d9e01df05e..b2a6baa7e8 100644 --- a/src/southbridge/intel/i82801gx/include/soc/nvs.h +++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h @@ -41,7 +41,7 @@ struct __packed global_nvs { u8 rsvd3[3]; /* Processor Identification */ u8 unused_was_apic; /* 0x28 - APIC enabled */ - u8 mpen; /* 0x29 - MP capable/enabled */ + u8 unused_was_mpen; /* 0x29 - MP capable/enabled */ u8 pcp0; /* 0x2a - PDC CPU/CORE 0 */ u8 pcp1; /* 0x2b - PDC CPU/CORE 1 */ u8 ppcm; /* 0x2c - Max. PPC state */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 6c48e9c906..a8bc7e3fa1 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -12,7 +12,6 @@ #include <device/pci_ops.h> #include <arch/ioapic.h> #include <acpi/acpi.h> -#include <acpi/acpi_gnvs.h> #include <cpu/x86/smm.h> #include <acpi/acpigen.h> #include <arch/smp/mpspec.h> @@ -21,7 +20,6 @@ #include <southbridge/intel/common/hpet.h> #include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/spi.h> -#include <soc/nvs.h> #include "chip.h" #include "i82801gx.h" @@ -464,12 +462,6 @@ static void lpc_final(struct device *dev) outb(POST_OS_BOOT, 0x80); } -void soc_fill_gnvs(struct global_nvs *gnvs) -{ - /* MPEN, Enable Multi Processing. */ - gnvs->mpen = dev_count_cpu() > 1 ? 1 : 0; -} - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; |