diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-28 13:24:15 +0200 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2019-07-08 14:53:32 +0000 |
| commit | b429c5be15dd4263e8ddb599e1e1f15dd95c3bf0 (patch) | |
| tree | d11ad98566d8a8a3d2a3e98cde1cc5ae8ca64cb1 /src/southbridge/intel/i82801gx | |
| parent | 92185e373ea70b4a9af6fb7f38b0855d7d898bf3 (diff) | |
sb/intel/i82801gx: Use common final SPI OPs setup
Change-Id: I30f80c237bccf8dc350249fd12ca6c4559d23d4f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 46 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 7 |
2 files changed, 2 insertions, 51 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 76420b4e17..fb855dc743 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -355,51 +355,5 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define C3_RES 0x54 #define TCO1_CNT 0x68 -/* SPIBAR - * - * SPI Opcode Menu setup for SPIBAR lockdown - * should support most common flash chips. - */ - -#define PREOP 0x54 -#define OPTYPE 0x56 -#define OPMENU 0x58 - -#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */ -#define SPI_OPTYPE_0 0x01 /* Write, no address */ - -#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */ -#define SPI_OPTYPE_1 0x03 /* Write, address required */ - -#define SPI_OPMENU_2 0x03 /* READ: Read Data */ -#define SPI_OPTYPE_2 0x02 /* Read, address required */ - -#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */ -#define SPI_OPTYPE_3 0x00 /* Read, no address */ - -#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */ -#define SPI_OPTYPE_4 0x03 /* Write, address required */ - -#define SPI_OPMENU_5 0x9f /* RDID: Read ID */ -#define SPI_OPTYPE_5 0x00 /* Read, no address */ - -#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */ -#define SPI_OPTYPE_6 0x03 /* Write, address required */ - -#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */ -#define SPI_OPTYPE_7 0x02 /* Read, address required */ - -#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \ - (SPI_OPMENU_5 << 8) | SPI_OPMENU_4) -#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \ - (SPI_OPMENU_1 << 8) | SPI_OPMENU_0) - -#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \ - (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \ - (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \ - (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0)) - -#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */ - #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index 846a70997b..6236ebd800 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -33,6 +33,7 @@ #include <drivers/intel/gma/i915.h> #include <southbridge/intel/common/acpi_pirq_gen.h> #include <southbridge/intel/common/pmbase.h> +#include <southbridge/intel/common/spi.h> #include "chip.h" #include "i82801gx.h" @@ -621,11 +622,7 @@ static void lpc_final(struct device *dev) if (!CONFIG(INTEL_CHIPSET_LOCKDOWN)) return; - SPIBAR16(PREOP) = SPI_OPPREFIX; - /* Set SPI opcode menu */ - SPIBAR16(OPTYPE) = SPI_OPTYPE; - SPIBAR32(OPMENU) = SPI_OPMENU_LOWER; - SPIBAR32(OPMENU + 4) = SPI_OPMENU_UPPER; + spi_finalize_ops(); /* Lock SPIBAR */ SPIBAR16(0) = SPIBAR16(0) | (1 << 15); |