diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-12-24 08:11:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-06-29 07:45:30 +0000 |
| commit | a8a9f34e9b7be8781c06c9d6fcc39f52bf31bd23 (patch) | |
| tree | b674190e4efe1c2a814a2638b3a20d92701c353d /src/southbridge/intel/i82801gx | |
| parent | e798e6a0b946fe5a3964bc38fb7783a219adf177 (diff) | |
sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables
Both southbridges need to be done at once since this southbridge code
is used for different northbridges, which fails to compile when done
separately.
This needs an acpi_name functions in the northbridge code to be
defined.
TESTED on Intel DG43GT: show correct PIRQ ACPI entries in
/sys/firmware/acpi/tables/SSDT.
Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/Kconfig | 1 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 13 |
2 files changed, 14 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig index 2670d23c9d..7e48848c7b 100644 --- a/src/southbridge/intel/i82801gx/Kconfig +++ b/src/southbridge/intel/i82801gx/Kconfig @@ -27,6 +27,7 @@ config SOUTHBRIDGE_INTEL_I82801GX select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select HAVE_INTEL_CHIPSET_LOCKDOWN + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ if SOUTHBRIDGE_INTEL_I82801GX diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index acc57a7dfb..ac83ec9500 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -32,6 +32,7 @@ #include <cbmem.h> #include <string.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #include "nvs.h" #define NMI_OFF 0 @@ -718,6 +719,16 @@ static void southbridge_inject_dsdt(struct device *dev) } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + +static void southbridge_fill_ssdt(device_t device) +{ + intel_acpi_gen_def_acpi_pirq(device); +} + static struct pci_operations pci_ops = { .set_subsystem = set_subsystem, }; @@ -728,6 +739,8 @@ static struct device_operations device_ops = { .enable_resources = pci_dev_enable_resources, .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, + .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .enable = i82801gx_enable, |