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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-09-21 18:35:37 +0300 |
|---|---|---|
| committer | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2019-10-01 01:54:08 +0000 |
| commit | df128a55b183d3d7a6d7ae986f33abffac50f371 (patch) | |
| tree | 66f2cef1c9f2516da2783cb945b99f8223e74046 /src/southbridge/intel/i82801gx | |
| parent | a84a7340b6291e209db2d5a3a28507816eec2223 (diff) | |
intel/pci: Utilise pci_def.h for PCI_BRIDGE_CONTROL
This is a PCI standard register, no need to alias its
definitions under different names.
Change-Id: Iea6b198dd70fe1e49b5dc0824dba62628dedc69a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/pci.c | 9 | ||||
| -rw-r--r-- | src/southbridge/intel/i82801gx/pcie.c | 10 |
3 files changed, 10 insertions, 13 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 7fc0114aac..d615b403ac 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -59,10 +59,6 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, #define SMLT 0x1b #define SECSTS 0x1e #define INTR 0x3c -#define BCTRL 0x3e -#define SBR (1 << 6) -#define SEE (1 << 1) -#define PERE (1 << 0) #define ICH_PCIE_DEV_SLOT 28 diff --git a/src/southbridge/intel/i82801gx/pci.c b/src/southbridge/intel/i82801gx/pci.c index 4d98e8939a..d493b790a7 100644 --- a/src/southbridge/intel/i82801gx/pci.c +++ b/src/southbridge/intel/i82801gx/pci.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "i82801gx.h" @@ -35,10 +36,10 @@ static void pci_init(struct device *dev) pci_write_config8(dev, INTR, 0xff); /* disable parity error response and SERR */ - reg16 = pci_read_config16(dev, BCTRL); - reg16 &= ~(1 << 0); - reg16 &= ~(1 << 1); - pci_write_config16(dev, BCTRL, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 &= ~PCI_BRIDGE_CTL_SERR; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Master Latency Count must be set to 0x04! */ reg8 = pci_read_config8(dev, SMLT); diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 0946a9aadf..0d8b474d9b 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -17,6 +17,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> #include "chip.h" @@ -67,11 +68,10 @@ static void pci_init(struct device *dev) // This has no effect but the OS might expect it pci_write_config8(dev, 0x0c, 0x10); - reg16 = pci_read_config16(dev, 0x3e); - reg16 &= ~(1 << 0); /* disable parity error response */ - // reg16 &= ~(1 << 1); /* disable SERR */ - reg16 |= (1 << 2); /* ISA enable */ - pci_write_config16(dev, 0x3e, reg16); + reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); + reg16 &= ~PCI_BRIDGE_CTL_PARITY; + reg16 |= PCI_BRIDGE_CTL_NO_ISA; + pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); /* Enable IO xAPIC on this PCIe port */ reg32 = pci_read_config32(dev, 0xd8); |