ACPI: Select ACPI_SOC_NVS only where suitable

Having some symmetry with <soc/nvs.h> now allows to reduce
the amount of gluelogic to determine the size and cbmc field
of struct global_nvs.

Since GNVS creation is now controlled by ACPI_SOC_NVS,
drivers/amd/agesa/nvs.c becomes obsolete and soc/amd/cezanne
cannot have this selected until <soc/nvs.h> exists.

Change-Id: Ia9ec853ff7f5e7908f7e8fc179ac27d0da08e19d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao

5 files changed, 5 insertions, 8 deletions

diff --git a/src/southbridge/intel/i82801gx/Kconfig b/src/southbridge/intel/i82801gx/Kconfig
index 2cd56e95ff..c8807935a2 100644
--- a/src/southbridge/intel/i82801gx/Kconfig
+++ b/src/southbridge/intel/i82801gx/Kconfig
@@ -3,6 +3,7 @@
 config SOUTHBRIDGE_INTEL_I82801GX
 	bool
 	select ACPI_INTEL_HARDWARE_SLEEP_VALUES
+	select ACPI_SOC_NVS
 	select AZALIA_PLUGIN_SUPPORT
 	select IOAPIC
 	select USE_WATCHDOG_ON_BOOT
diff --git a/src/southbridge/intel/i82801gx/Makefile.inc b/src/southbridge/intel/i82801gx/Makefile.inc
index 11a9c0007d..95402a1dfc 100644
--- a/src/southbridge/intel/i82801gx/Makefile.inc
+++ b/src/southbridge/intel/i82801gx/Makefile.inc
@@ -25,4 +25,6 @@ smm-y += smihandler.c
 romstage-y += early_init.c
 romstage-y += early_cir.c
 
+CPPFLAGS_common += -I$(src)/southbridge/intel/i82801gx/include
+
 endif
diff --git a/src/southbridge/intel/i82801gx/nvs.h b/src/southbridge/intel/i82801gx/include/soc/nvs.h
index b23b85bec2..b23b85bec2 100644
--- a/src/southbridge/intel/i82801gx/nvs.h
+++ b/src/southbridge/intel/i82801gx/include/soc/nvs.h
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c
index 74cadc8df4..4b7898c75e 100644
--- a/src/southbridge/intel/i82801gx/lpc.c
+++ b/src/southbridge/intel/i82801gx/lpc.c
@@ -21,10 +21,10 @@
 #include <southbridge/intel/common/hpet.h>
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/common/spi.h>
+#include <soc/nvs.h>
 
 #include "chip.h"
 #include "i82801gx.h"
-#include "nvs.h"
 
 #define NMI_OFF	0
 
@@ -464,11 +464,6 @@ static void lpc_final(struct device *dev)
 	outb(POST_OS_BOOT, 0x80);
 }
 
-size_t gnvs_size_of_array(void)
-{
-	return sizeof(struct global_nvs);
-}
-
 void soc_fill_gnvs(struct global_nvs *gnvs)
 {
 	gnvs->apic = 1;
diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c
index 03480a7903..67a8cf8cf4 100644
--- a/src/southbridge/intel/i82801gx/smihandler.c
+++ b/src/southbridge/intel/i82801gx/smihandler.c
@@ -4,6 +4,7 @@
 #include <console/console.h>
 #include <cpu/x86/smm.h>
 #include <device/pci_def.h>
+#include <soc/nvs.h>
 #include <southbridge/intel/common/pmutil.h>
 #include "i82801gx.h"
 
@@ -15,8 +16,6 @@
 #define   G_SMRANE	(1 << 3)
 #define   C_BASE_SEG	((0 << 2) | (1 << 1) | (0 << 0))
 
-#include "nvs.h"
-
 /* While we read PMBASE dynamically in case it changed, let's initialize it with a sane value */
 u16 pmbase = DEFAULT_PMBASE;