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| author | Andrey Petrov <andrey.petrov@intel.com> | 2016-11-04 16:17:11 -0700 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2016-11-30 16:45:53 +0100 |
| commit | 4ed99ad067a7bd9f5ef6004c7b0e5f9f7edbe0d5 (patch) | |
| tree | c9e937ce5dd45d6e443651a36f295da431d1f8c4 /src/southbridge/intel/i82801gx/smi.c | |
| parent | f796c6e0ec6769873d63b6fcfc64c0ac14ba3555 (diff) | |
mainboard/reef: Add RW_VAR_MRC_CACHE
Chop off 4kb block from RW_MRC_CACHE to store variable MRC cache.
BUG=chrome-os-partner:57515
TEST=with patch series applied: cold reboot, make sure MRC is not
updated. Do S3 suspend/resume cycle.
Change-Id: I3e19fff9c9b20d6c73cbb13bfeec49e9a274bb72
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/17235
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/smi.c')
0 files changed, 0 insertions, 0 deletions