diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-04-27 05:08:26 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2020-05-01 11:51:08 +0000 |
| commit | 1234925ad77aa888fb28034251b950e1bc2fd480 (patch) | |
| tree | b3744dffd92a6baaeb11f2302a1e532d2fc2e251 /src/southbridge/intel/i82801gx/pcie.c | |
| parent | 38df060abad3ac105d73fc7425c89571650b40f1 (diff) | |
sb/intel/i82801gx: Fix 16-bit read/write PCI_COMMAND register
Change-Id: I11b8743234cb1292db8c930edecf8fb5c47d63fd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/pcie.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/pcie.c | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 4398ad56b0..4de62e256d 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -47,9 +47,7 @@ static void pci_init(struct device *dev) printk(BIOS_DEBUG, "Initializing ICH7 PCIe bridge.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it |