diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-05-21 09:04:16 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:12:19 +0000 |
| commit | ae22fe293fc97a9f6b0fbf52230277b2a4332cda (patch) | |
| tree | cae4d7cb79e527ba92b8a3ce1022c14693e77a4b /src/southbridge/intel/i82801gx/pcie.c | |
| parent | 2f2191a3d0876fb90ab0c5f09e1c802b0a89b83e (diff) | |
sb/intel/i82801gx: Use macro instead of numbers
Change-Id: Ide6516937ea79c35cd54127ed2823352a1cac6d4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41611
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/pcie.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/pcie.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index 56cf1f287d..7a49e52859 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -50,7 +50,7 @@ static void pci_init(struct device *dev) /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it - pci_write_config8(dev, 0x0c, 0x10); + pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 0x10); reg16 = pci_read_config16(dev, PCI_BRIDGE_CONTROL); reg16 &= ~PCI_BRIDGE_CTL_PARITY; |