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| author | Sean Rhodes <sean@starlabs.systems> | 2024-07-31 20:47:57 +0100 |
|---|---|---|
| committer | Sean Rhodes <sean@starlabs.systems> | 2024-10-11 08:32:18 +0000 |
| commit | abe2e62f62e5a5902efa8ca0f63fcf87e477bffc (patch) | |
| tree | 6aa1fb79cf66f5bd4d517500c91b9604f85125d7 /src/southbridge/intel/i82801gx/pci.c | |
| parent | b0128b18b58699ee3923314e6a95d6eadcd11544 (diff) | |
soc/intel/cnvi: Add CFLR Method
This method is used to limit frequencies on CNVi.
Intel document #559910 details this.
Change-Id: Idc4c35e71076fd31786212995472bb8d58c961de
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/pci.c')
0 files changed, 0 insertions, 0 deletions