diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2021-05-04 23:36:36 +0530 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-05-06 14:39:06 +0000 |
| commit | a2cf34129fb3b2a9302bb7cf06e4ee758b9bb85a (patch) | |
| tree | a80ebde191b4bb5ab279756a52b67b46ab308b4d /src/southbridge/intel/i82801gx/lpc.c | |
| parent | 88a0ce6e11601678ec8d8f6a87c4881b810cb5df (diff) | |
include/console: Align ramstage Boot State Machine postcodes
This patch ensures all boot state machine postcodes are in right
order. Move POST_ENTRY_RAMSTAGE macro definition after
POST_BS_PAYLOAD_BOOT.
Change-Id: I9e03159fdf07a73f5f8eec1bbf32fcb47dd4af84
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52893
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/lpc.c')
0 files changed, 0 insertions, 0 deletions