diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2018-05-13 12:47:28 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-05-22 07:22:01 +0000 |
| commit | 996670377666eac27af4c4562d48677305e4e937 (patch) | |
| tree | f70c430db822c42e9d44686836ec8937503b4aee /src/southbridge/intel/i82801gx/lpc.c | |
| parent | cbcdb3e754a2d1c68928725d37ccf1621d936a74 (diff) | |
sb/intel/i82801gx: Get rid of device_t
Use of device_t has been abandoned in ramstage.
Change-Id: Iccddf3140fd94c2e5a246fe2839573f5dd387147
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/lpc.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index a26b9f8a8e..ab426ab86c 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -88,9 +88,9 @@ static void i82801gx_enable_serial_irqs(struct device *dev) * 0x80 - The PIRQ is not routed. */ -static void i82801gx_pirq_init(device_t dev) +static void i82801gx_pirq_init(struct device *dev) { - device_t irq_dev; + struct device *irq_dev; /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -134,7 +134,7 @@ static void i82801gx_pirq_init(device_t dev) } } -static void i82801gx_gpi_routing(device_t dev) +static void i82801gx_gpi_routing(struct device *dev) { /* Get the chip configuration */ config_t *config = dev->chip_info; @@ -163,7 +163,7 @@ static void i82801gx_gpi_routing(device_t dev) pci_write_config32(dev, GPIO_ROUT, reg32); } -static void i82801gx_power_options(device_t dev) +static void i82801gx_power_options(struct device *dev) { u8 reg8; u16 reg16, pmbase; @@ -267,7 +267,7 @@ static void i82801gx_power_options(device_t dev) outl(reg32, pmbase + 0x04); } -static void i82801gx_configure_cstates(device_t dev) +static void i82801gx_configure_cstates(struct device *dev) { u8 reg8; @@ -487,7 +487,7 @@ unsigned long acpi_fill_madt(unsigned long current) void acpi_fill_fadt(acpi_fadt_t *fadt) { - device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); + struct device *dev = dev_find_slot(0, PCI_DEVFN(0x1f, 0)); config_t *chip = dev->chip_info; u16 pmbase = pci_read_config16(dev, 0x40) & 0xfffe; @@ -603,7 +603,7 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= ACPI_FADT_DOCKING_SUPPORTED; } -static void i82801gx_lpc_read_resources(device_t dev) +static void i82801gx_lpc_read_resources(struct device *dev) { struct resource *res; u8 io_index = 0; @@ -645,8 +645,8 @@ static void i82801gx_lpc_read_resources(device_t dev) } } -static void set_subsystem(device_t dev, unsigned int vendor, - unsigned int device) +static void set_subsystem(struct device *dev, unsigned int vendor, + unsigned int device) { if (!vendor || !device) { pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID, @@ -657,7 +657,7 @@ static void set_subsystem(device_t dev, unsigned int vendor, } } -static void southbridge_inject_dsdt(device_t dev) +static void southbridge_inject_dsdt(struct device *dev) { global_nvs_t *gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); |