Support for the Intel ICH7 southbridge.

This includes an early SMI handler.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 122 insertions, 0 deletions

diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
new file mode 100644
index 0000000000..1601dc3d71
--- /dev/null
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -0,0 +1,122 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
+#define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
+
+#include "chip.h"
+extern void i82801gx_enable(device_t dev);
+
+#define PCI_DMA_CFG		0x90
+#define SERIRQ_CNTL		0x64
+#define GEN_CNTL		0xd0
+#define GEN_STS			0xd4
+#define RTC_CONF		0xd8
+#define GEN_PMCON_1		0xa0
+#define GEN_PMCON_2		0xa2
+#define GEN_PMCON_3		0xa4
+
+#define PMBASE			0x40
+#define ACPI_CNTL		0x44
+#define BIOS_CNTL		0x4E
+#define GPIO_BASE		0x48 /* LPC GPIO Base Address Register */
+#define GPIO_CNTL		0x4C /* LPC GPIO Control Register */
+
+#define PIRQA_ROUT		0x60
+#define PIRQB_ROUT		0x61
+#define PIRQC_ROUT		0x62
+#define PIRQD_ROUT		0x63
+#define PIRQE_ROUT		0x68
+#define PIRQF_ROUT		0x69
+#define PIRQG_ROUT		0x6A
+#define PIRQH_ROUT		0x6B
+
+#define FUNC_DIS		0xF2
+
+#define LPC_IO_DEC		0x80 /* IO Decode Ranges Register */
+#define LPC_EN			0x82 /* LPC IF Enables Register */
+
+#define SBUS_NUM		0x19
+#define SUB_BUS_NUM		0x1A
+#define SMLT			0x1B
+#define IOBASE			0x1C
+#define IOLIM			0x1D
+#define MEMBASE			0x20
+#define MEMLIM			0x22
+#define CNF			0x50
+#define MTT			0x70
+#define PCI_MAST_STS		0x82
+
+/* GEN_PMCON_3 bits */
+#define RTC_BATTERY_DEAD	(1 << 2)
+#define RTC_POWER_FAILED	(1 << 1)
+#define SLEEP_AFTER_POWER_FAIL	(1 << 0)
+
+/* PCI Configuration Space (D31:F1) */
+#define INTR_LN			0x3c
+#define IDE_TIM_PRI		0x40	/* IDE timings, primary */
+#define   IDE_DECODE_ENABLE	(1 << 15)
+#define   IDE_SITRE		(1 << 14)
+#define IDE_TIM_SEC		0x42	/* IDE timings, secondary */
+#define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
+#define   SIG_MODE_NORMAL	(0 << 16)
+#define   SIG_MODE_TRISTATE	(1 << 16)
+#define   SIG_MODE_DRIVELOW	(2 << 16)
+#define   FAST_PCB1		(1 << 13)
+#define   FAST_PCB0		(1 << 12)
+#define   PCB1			(1 <<  1)
+#define   PCB0			(1 <<  0)
+
+/* PCI Configuration Space (D31:F3) */
+#define SMB_BASE		0x20
+#define HOSTC			0x40
+
+/* HOSTC bits */
+#define I2C_EN			(1 << 2)
+#define SMB_SMI_EN		(1 << 1)
+#define HST_EN			(1 << 0)
+
+/* SMBus I/O bits.
+ * TODO: It does not matter where we put the SMBus IO base, as long as we keep
+ * consistent and don't interfere with other devices. Stage2 will relocate 
+ * this anyways. But it's a general problem we have not solved in the brightest
+ * possible way.
+ */
+/* #define SMBUS_IO_BASE 0x1000 */
+#define SMBUS_IO_BASE		0x0400
+
+#define SMBHSTSTAT		0x0
+#define SMBHSTCTL		0x2
+#define SMBHSTCMD		0x3
+#define SMBXMITADD		0x4
+#define SMBHSTDAT0		0x5
+#define SMBHSTDAT1		0x6
+#define SMBBLKDAT		0x7
+#define SMBTRNSADD		0x9
+#define SMBSLVDATA		0xa
+#define SMLINK_PIN_CTL		0xe
+#define SMBUS_PIN_CTL		0xf
+
+#define SMBUS_TIMEOUT		(10 * 1000 * 100)
+
+/* HPET, if present */
+#define HPET_ADDR		0xfed0000
+
+#endif				/* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */