diff options
| author | Stefan Reinauer <stepan@coresystems.de> | 2010-01-17 13:49:07 +0000 |
|---|---|---|
| committer | Stefan Reinauer <stepan@openbios.org> | 2010-01-17 13:49:07 +0000 |
| commit | 7a3d09521370d493c377955db9f1fa8c5dbb55bb (patch) | |
| tree | 8cd4c4c711f108bdc24871171d99410541031b16 /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | 24b4df5f9904216e1651b087e4e7a57f8d5220f9 (diff) | |
ICH7 update
* change the code to use macros names instead of constants in many places
* SMI/ACPI: rework power-off code to work with old Linux kernels (2.6.12.x)
* SMI: Add support for mainboard GPI handler
* SMI: immediate power-off on power button press, if OSPM is not active
* Add fix for some USB errata
* Some register tweaks for mobile systems
* Enable configure SCI on interrupt 9 correctly.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5026 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 5c29c9ea62..8f62c1be2c 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -32,6 +32,8 @@ /* TODO Make sure these don't get changed by stage2 */ #define DEFAULT_GPIOBASE 0x0480 #define DEFAULT_PMBASE 0x0500 + +#define IO_APIC_ADDR 0xfec00000 #define HPET_ADDR 0xfed00000 #define DEFAULT_RCBA 0xfed1c000 @@ -276,7 +278,20 @@ extern void i82801gx_enable(device_t dev); /* ICH7 PMBASE */ #define PM1_STS 0x00 +#define WAK_STS (1 << 15) +#define PCIEXPWAK_STS (1 << 14) +#define PRBTNOR_STS (1 << 11) +#define RTC_STS (1 << 10) +#define PWRBTN_STS (1 << 8) +#define GBL_STS (1 << 5) +#define BM_STS (1 << 4) +#define TMROF_STS (1 << 0) #define PM1_EN 0x02 +#define PCIEXPWAK_DIS (1 << 14) +#define RTC_EN (1 << 10) +#define PWRBTN_EN (1 << 8) +#define GBL_EN (1 << 5) +#define TMROF_EN (1 << 0) #define PM1_CNT 0x04 #define SLP_EN (1 << 13) #define SLP_TYP (7 << 10) @@ -290,8 +305,24 @@ extern void i82801gx_enable(device_t dev); #define LV4 0x16 #define PM2_CNT 0x20 // mobile only #define GPE0_STS 0x28 +#define USB4_STS (1 << 14) +#define PME_B0_STS (1 << 13) +#define USB3_STS (1 << 12) +#define PME_STS (1 << 11) +#define BATLOW_STS (1 << 10) +#define PCI_EXP_STS (1 << 9) +#define RI_STS (1 << 8) +#define SMB_WAK_STS (1 << 7) +#define TCOSCI_STS (1 << 6) +#define AC97_STS (1 << 5) +#define USB2_STS (1 << 4) +#define USB1_STS (1 << 3) +#define SWGPE_STS (1 << 2) +#define HOT_PLUG_STS (1 << 1) +#define THRM_STS (1 << 0) #define GPE0_EN 0x2c #define PME_B0_EN (1 << 13) +#define PME_EN (1 << 11) #define SMI_EN 0x30 #define EL_SMI_EN (1 << 25) // Intel Quick Resume Technology #define INTEL_USB2_EN (1 << 18) // Intel-Specific USB2 SMI logic |