Kontron 986LCD-M update

- run ACPI code through preprocessor so we get the same values
  as the C code
- fix PCIe x16 slot
- fix ICH7 Azalia/HDA driver
- SMI/GNVS update security fix (only allow struct pointer update once)
- ACPI updates
- IDE driver fixes
- add cmos options for disabling onboard ethernet and controlling system fan

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

1 files changed, 80 insertions, 19 deletions

diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h
index 98c62ce091..9b54fc6008 100644
--- a/src/southbridge/intel/i82801gx/i82801gx.h
+++ b/src/southbridge/intel/i82801gx/i82801gx.h
@@ -20,6 +20,23 @@
 
 #ifndef SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
 #define SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H
+/*
+ * It does not matter where we put the SMBus I/O base, as long as we
+ * keep it consistent and don't interfere with other devices.  Stage2
+ * will relocate this anyways.
+ * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
+ * again. But handling static BARs is a generic problem that should be
+ * solved in the device allocator.
+ */
+#define SMBUS_IO_BASE		0x0400
+/* TODO Make sure these don't get changed by stage2 */
+#define DEFAULT_GPIOBASE	0x0480
+#define DEFAULT_PMBASE		0x0500
+#define HPET_ADDR		0xfed00000
+#define DEFAULT_RCBA		0xfed1c000
+
+#ifndef __ACPI__
+#define DEBUG_PERIODIC_SMIS 0
 
 /* __ROMCC__ is set by auto.c to make sure
  * none of the stage2 data structures are included.
@@ -91,11 +108,18 @@ extern void i82801gx_enable(device_t dev);
 #define IDE_SDMA_TIM		0x4a
 
 #define IDE_CONFIG		0x54	/* IDE I/O Configuration Register */
-#define   SIG_MODE_NORMAL	(0 << 16)
-#define   SIG_MODE_TRISTATE	(1 << 16)
-#define   SIG_MODE_DRIVELOW	(2 << 16)
+#define   SIG_MODE_SEC_NORMAL	(0 << 18)
+#define   SIG_MODE_SEC_TRISTATE	(1 << 18)
+#define   SIG_MODE_SEC_DRIVELOW	(2 << 18)
+#define   SIG_MODE_PRI_NORMAL	(0 << 16)
+#define   SIG_MODE_PRI_TRISTATE	(1 << 16)
+#define   SIG_MODE_PRI_DRIVELOW	(2 << 16)
+#define   FAST_SCB1		(1 << 15)
+#define   FAST_SCB0		(1 << 14)
 #define   FAST_PCB1		(1 << 13)
 #define   FAST_PCB0		(1 << 12)
+#define   SCB1			(1 <<  3)
+#define   SCB0			(1 <<  2)
 #define   PCB1			(1 <<  1)
 #define   PCB0			(1 <<  0)
 
@@ -108,16 +132,7 @@ extern void i82801gx_enable(device_t dev);
 #define SMB_SMI_EN		(1 << 1)
 #define HST_EN			(1 << 0)
 
-/* SMBus I/O bits.
- * It does not matter where we put the SMBus I/O base, as long as we
- * keep it consistent and don't interfere with other devices.  Stage2
- * will relocate this anyways.
- * Our solution is to have SMB initialization move the I/O to SMBUS_IO_BASE
- * again. But handling static BARs is a generic problem that should be
- * solved in the device allocator.
- */
-#define SMBUS_IO_BASE		0x0400
-
+/* SMBus I/O bits. */
 #define SMBHSTSTAT		0x0
 #define SMBHSTCTL		0x2
 #define SMBHSTCMD		0x3
@@ -132,21 +147,15 @@ extern void i82801gx_enable(device_t dev);
 
 #define SMBUS_TIMEOUT		(10 * 1000 * 100)
 
-/* HPET, if present */
-#define HPET_ADDR		0xfed0000
 
 /* Southbridge IO BARs */
 
-/* TODO Make sure these don't get changed by stage2 */
 #define GPIOBASE		0x48
-#define DEFAULT_GPIOBASE	0x480
 
 #define PMBASE		0x40
-#define DEFAULT_PMBASE	0x500
 
 /* Root Complex Register Block */
 #define RCBA		0xf0
-#define DEFAULT_RCBA		0xfed1c000
 
 #define RCBA8(x) *((volatile u8 *)(DEFAULT_RCBA + x))
 #define RCBA16(x) *((volatile u16 *)(DEFAULT_RCBA + x))
@@ -255,4 +264,56 @@ extern void i82801gx_enable(device_t dev);
 #define FD_SATA		(1 <<  2)
 #define FD_PATA		(1 <<  1)
 
+/* ICH7 GPIOBASE */
+#define GPIO_USE_SEL	0x00
+#define GP_IO_SEL	0x04
+#define GP_LVL		0x0c
+#define GPO_BLINK	0x18
+#define GPI_INV		0x2c
+#define GPIO_USE_SEL2	0x30
+#define GP_IO_SEL2	0x34
+#define GP_LVL2		0x38
+
+/* ICH7 PMBASE */
+#define PM1_STS		0x00
+#define PM1_EN		0x02
+#define PM1_CNT		0x04
+#define   SLP_EN	(1 << 13)
+#define   SLP_TYP	(7 << 10)
+#define   GBL_RLS	(1 << 2)
+#define   BM_RLD	(1 << 1)
+#define   SCI_EN	(1 << 0)
+#define PM1_TMR		0x08
+#define PROC_CNT	0x10
+#define LV2		0x14
+#define LV3		0x15
+#define LV4		0x16
+#define PM2_CNT		0x20 // mobile only
+#define GPE0_STS	0x28
+#define GPE0_EN		0x2c
+#define   PME_B0_EN	(1 << 13)
+#define SMI_EN		0x30
+#define   EL_SMI_EN	 (1 << 25) // Intel Quick Resume Technology
+#define   INTEL_USB2_EN	 (1 << 18) // Intel-Specific USB2 SMI logic
+#define   LEGACY_USB2_EN (1 << 17) // Legacy USB2 SMI logic
+#define   PERIODIC_EN	 (1 << 14) // SMI on PERIODIC_STS in SMI_STS
+#define   TCO_EN	 (1 << 13) // Enable TCO Logic (BIOSWE et al)
+#define   MCSMI_EN	 (1 << 11) // Trap microcontroller range access
+#define   BIOS_RLS	 (1 <<  7) // asserts SCI on bit set
+#define   SWSMI_TMR_EN	 (1 <<  6) // start software smi timer on bit set
+#define   APMC_EN	 (1 <<  5) // Writes to APM_CNT cause SMI#
+#define   SLP_SMI_EN	 (1 <<  4) // Write to SLP_EN in PM1_CNT asserts SMI#
+#define   LEGACY_USB_EN  (1 <<  3) // Legacy USB circuit SMI logic
+#define   BIOS_EN	 (1 <<  2) // Assert SMI# on setting GBL_RLS bit
+#define   EOS		 (1 <<  1) // End of SMI (deassert SMI#)
+#define   GBL_SMI_EN	 (1 <<  0) // SMI# generation at all?
+#define SMI_STS		0x34
+#define ALT_GP_SMI_EN	0x38
+#define ALT_GP_SMI_STS	0x3a
+#define GPE_CNTL	0x42
+#define DEVACT_STS	0x44
+#define SS_CNT		0x50
+#define C3_RES		0x54
+
+#endif /* __ACPI__ */
 #endif				/* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */