diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2018-12-20 01:44:50 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-01-17 14:53:08 +0000 |
| commit | e6e5ecb7e813fa151c558c739d5394dce0a2af8e (patch) | |
| tree | 5227024409ee0826db078d98aee3a61a1204c352 /src/southbridge/intel/i82801gx/i82801gx.h | |
| parent | 7bbe3bb9f0caf518af89bc18b99cd9ac32ceff3f (diff) | |
sb/intel/i82801gx: Implement PCIe coalescing
The implementation is a simplified version of the haswell/broadwell
code. This also adds a chip option to enable coalescing from the
devicetree.
Change-Id: I6d7ddef96e4f45e163f7017175398a0938a18273
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Diffstat (limited to 'src/southbridge/intel/i82801gx/i82801gx.h')
| -rw-r--r-- | src/southbridge/intel/i82801gx/i82801gx.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 395cdd13cf..e664eb43fa 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -84,6 +84,9 @@ int southbridge_detect_s3_resume(void); #define GPI_IS_SCI 0x02 #define GPI_IS_NMI 0x03 +#define FDVCT 0xe4 +#define PCIE_4_PORTS_MAX (1 << 7) + /* GEN_PMCON_3 bits */ #define RTC_BATTERY_DEAD (1 << 2) #define RTC_POWER_FAILED (1 << 1) |