diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2017-03-09 12:02:52 +0100 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2017-03-22 17:55:53 +0100 |
| commit | 3f111b0b11cf3d14b9aded601b6a1dd84f35a8dc (patch) | |
| tree | a11b02549c808bd7a59ee762a73bd46561731ea3 /src/southbridge/intel/i82801gx/early_lpc.c | |
| parent | 70a8e34853d4b01ab7a2089821c35715c59b4415 (diff) | |
southbridge/intel/i82801gx: Fix problems found by checkpatch.pl
Change-Id: Iddc67e7c126ce19429afc24b021e385353564cb8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18705
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/early_lpc.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/early_lpc.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/southbridge/intel/i82801gx/early_lpc.c b/src/southbridge/intel/i82801gx/early_lpc.c index 4aa9f10297..11da3ec4b1 100644 --- a/src/southbridge/intel/i82801gx/early_lpc.c +++ b/src/southbridge/intel/i82801gx/early_lpc.c @@ -38,15 +38,15 @@ int southbridge_detect_s3_resume(void) reg32 = inl(DEFAULT_PMBASE + 0x04); printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32); if (((reg32 >> 10) & 7) == 5) { - if (acpi_s3_resume_allowed()) { + if (!acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } else { printk(BIOS_DEBUG, "Resume from S3 detected.\n"); /* Clear SLP_TYPE. This will break stage2 but * we care for that when we get there. */ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); return 1; - } else { - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); } } |