summaryrefslogtreecommitdiff
path: root/src/southbridge/intel/i82801gx/chip.h
diff options
context:
space:
mode:
authorVladimir Serbinenko <phcoder@gmail.com>2014-10-25 15:18:25 +0200
committerVladimir Serbinenko <phcoder@gmail.com>2014-11-04 23:02:27 +0100
commitab83ef02c7131d23a28c6acbd79e6cd9997dcec8 (patch)
tree2a04f314104c3a43e6eaaacd5cceb5ec8db81386 /src/southbridge/intel/i82801gx/chip.h
parent9c4f1b8e05fbd659ebdb3d03d811f1ad39079a1a (diff)
i82801gx: Handle whole FADT in southbridge.
Do all the handling in SB code with few parameters from devicetree.cb instead of having mobo callbacks. Change-Id: I8fd02ff05553a3c51ea5f6ae66b8f5502509e2bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/7199 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/chip.h')
-rw-r--r--src/southbridge/intel/i82801gx/chip.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h
index 76fc90ee59..2bb81d6ce5 100644
--- a/src/southbridge/intel/i82801gx/chip.h
+++ b/src/southbridge/intel/i82801gx/chip.h
@@ -71,6 +71,9 @@ struct southbridge_intel_i82801gx_config {
uint32_t sata_ports_implemented;
int c4onc3_enable:1;
+ int docking_supported:1;
+ int p_cnt_throttling_supported:1;
+ int c3_latency;
};
#endif /* SOUTHBRIDGE_INTEL_I82801GX_CHIP_H */