diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-09 14:19:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-12 18:22:57 +0000 |
| commit | fecf77770b8e68b9ef82021ca53c31db93736d93 (patch) | |
| tree | 001fba539061f4075699fc98e02b3153259477e9 /src/southbridge/intel/i82801gx/bootblock_gcc.c | |
| parent | 675cb9152e6704383cf402c55758ddea2c7a1e05 (diff) | |
sb/intel/i82801gx: Add common LPC decode code
Generic LPC decode ranges can now be set from the devicetree.
Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/bootblock_gcc.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock_gcc.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock_gcc.c b/src/southbridge/intel/i82801gx/bootblock_gcc.c index 996788888a..063a461e43 100644 --- a/src/southbridge/intel/i82801gx/bootblock_gcc.c +++ b/src/southbridge/intel/i82801gx/bootblock_gcc.c @@ -41,4 +41,6 @@ void bootblock_early_southbridge_init(void) /* Disable watchdog timer */ RCBA32(GCS) = RCBA32(GCS) | 0x20; + + i82801gx_lpc_setup(); } |