diff options
| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-11-12 23:34:13 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-11-15 16:45:48 +0000 |
| commit | e27c013f39f0433dac57a754b3484553a536f30d (patch) | |
| tree | 6e9b9d20964ac994c453079ca9c13cb145480dbd /src/southbridge/intel/i82801gx/bootblock.c | |
| parent | dc584c3f221bb59ee6b89e5517617b9d1d74bcf3 (diff) | |
nb/intel/i945: Move to C_ENVIRONMENT_BOOTBLOCK
Console init in bootblock will be done in a separate CL.
Change-Id: Ia2405013f262d904aa82be323e928223dbb4296c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36795
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/southbridge/intel/i82801gx/bootblock.c')
| -rw-r--r-- | src/southbridge/intel/i82801gx/bootblock.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/src/southbridge/intel/i82801gx/bootblock.c b/src/southbridge/intel/i82801gx/bootblock.c index 9d94d0cd25..4c464ff920 100644 --- a/src/southbridge/intel/i82801gx/bootblock.c +++ b/src/southbridge/intel/i82801gx/bootblock.c @@ -14,14 +14,13 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> #include "i82801gx.h" static void enable_spi_prefetch(void) { u8 reg8; - pci_devfn_t dev; - - dev = PCI_DEV(0, 0x1f, 0); + pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); reg8 = pci_read_config8(dev, BIOS_CNTL); reg8 &= ~(3 << 2); @@ -29,13 +28,17 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, BIOS_CNTL, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, (uintptr_t)DEFAULT_RCBA | 1); + i82801gx_setup_bars(); /* Enable upper 128bytes of CMOS */ RCBA32(0x3400) = (1 << 2); + + /* Disable watchdog timer */ + RCBA32(GCS) = RCBA32(GCS) | 0x20; + + i82801gx_lpc_setup(); } |