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| author | Kyösti Mälkki <kyosti.malkki@gmail.com> | 2021-01-27 20:25:51 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2021-02-01 08:54:31 +0000 |
| commit | 0b7446a2694ef8ad8c480602a7aee9ad90810ac7 (patch) | |
| tree | 8a3b558010219a6f6844dcb652d581f26f2bae4e /src/southbridge/intel/i82801gx/acpi | |
| parent | da321d883468f1306dc6105d3d924b12cb43fa06 (diff) | |
sb/intel/i82801gx,ix: Drop MPEN from GNVS
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: I3928e5973fe65d9a4fe7975e5d5584efe6e5f2f8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Diffstat (limited to 'src/southbridge/intel/i82801gx/acpi')
| -rw-r--r-- | src/southbridge/intel/i82801gx/acpi/globalnvs.asl | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl index dfd5a560c8..1e3889b4f5 100644 --- a/src/southbridge/intel/i82801gx/acpi/globalnvs.asl +++ b/src/southbridge/intel/i82801gx/acpi/globalnvs.asl @@ -45,7 +45,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Processor Identification */ Offset (0x28), , 8, // 0x28 - Enabled by coreboot - MPEN, 8, // 0x29 - Multi Processor Enable + , 8, // 0x29 - Multi Processor Enable PCP0, 8, // 0x2a - PDC CPU/CORE 0 PCP1, 8, // 0x2b - PDC CPU/CORE 1 PPCM, 8, // 0x2c - Max. PPC state |